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[AK4430] ms1196-e-01 2011/03 - 1 - AK4430 192khz 24-bit stereo ? dac with 2vrms output general description the AK4430 is 3.3v 24-bit stereo dac with an integrated 2vrms output buffer. a charge pump in the buffer develops an internal negative power supply rail that enables a ground-referenced 2vrms output. using akm?s multi bit modulator architecture, t he AK4430 delivers a wide dynamic range while preserving linearity for improved thd+n perform ance. the AK4430 integrates a comb ination of swit ched-capacitor and continuous-time filters, increasing performance for systems with excessive clock jitter. the 24-bit word length and 192khz sampling rate make this part ideal for a wide range of consumer audio applications, such as portable a/v pl ayers, set-top boxes, and digital televisions. the AK4430 is offered in a space saving 16pin tssop package. features ? sampling rate ranging from 8khz to 192khz ? 128 times oversampling (normal speed mode) ? 64 times oversampling (double speed mode) ? 32 times oversampling (quad speed mode) ? 24-bit 8 times fir digital filter ? switched-capacitor filter with high tolerance to clock jitter ? single ended 2vrms output buffer ? soft mute ? i/f format: 24-bit msb justified, i 2 s ? master clock: 512fs, 768fs or 1152fs (normal speed mode) 256fs or 384fs (double speed mode) 128fs or 192fs (quad speed mode) ? thd+n: -91db ? dynamic range: 104db ? automatic power-on reset circuit ? power supply: +3.0 +3.6v ? ta = -20 to 85 c ? small package: 16pin tssop (6.4mm x 5.0mm) lrck bick sdti audio data interface mclk ? modulator aoutl 8x interpolator scf lpf aoutr vdd vss1 control interface clock divider ? 8x interpolator scf lpf charge pump cp cn vee vss2 cvdd 1 1 vrefh smute dif modulator 2.2
[AK4430] ordering guide AK4430et -20 +85 c 16pin tssop (0.65mm pitch) akd4430 evaluation board for AK4430 pin layout 6 5 4 3 2 1 cn cp mclk smute bick sdti 7 dif 8 vee vss2 cvdd vrefh vss1 vdd aoutl aoutr AK4430 top view 11 12 13 14 15 16 10 9 lrck compatibility with the ak4420, ak4424, ak4421 and ak4421a ak4420 ak4424 ak4421 ak4421a AK4430 power supply +4.5 +5.5v +4.5 +5.5v +3.0 +3.6v +3.0 +3.6v +3.0 +3.6v digital de-emphasis - x - - - i/f format 24-bit msb/i 2 s i 2 s 24-bit msb/i 2 s 24-bit msb/i 2 s 24-bit msb/i 2 s pin out pin#3 smute dem smute smute smute pin#8 dif smute dif dif* dif* pin#13 dzf dzf dzf dzf vrefh thd+n -92db -92db -92db (-3dbfs) -92db -91db dr 105db 105db 102db 102db 104db operating temperature et: -20 +85 c vt: -40 +85 c et: -20 +85 c et: -20 +85 c et: -20 +85 c et: -20 +85 c (-: not available, x: available) *: internal pull up (100k ? ) ms1196-e-01 2011/03 - 2 -
[AK4430] pin/function no. pin name i/o function 1 cn i negative charge pump capacitor terminal pin connect to cp with a 1.0 f low esr (equivalent series resistance) capacitor over temperature. when this capacitor is polarized, the positive polarity pin should be connected to the cp pin. non-polarized capacitors can also be used. 2 cp i positive charge pump capacitor terminal pin connect to cn with a 1.0 f low esr (equivalent series resistance) capacitor over temperature. when this capacitor is polarized, the positive polarity pin should be connected to the cp pin. non-polarized capacitors can also be used. 3 smute i soft mute enable pin (internal pull down: 100k ? ) ?h?: enable, ?l?: disable 4 mclk i master clock input pin 5 bick i audio serial data clock pin 6 sdti i audio serial data input pin 7 lrck i l/r clock pin 8 dif i audio data interface format pin (internal pull up: 100k ) ?l?: 24-bit msb justified, ?h?: i 2 s, 9 aoutr o right channel analog output pin when mclk or lrck or bick stops, outputs vss(0v, typ). 10 aoutl o left channel analog output pin when mclk or lrck or bick stops, outputs vss(0v, typ). 11 vdd - power supply pin, 3.0v 3.6v 12 vss1 - ground pin 1 13 vrefh o reference output pin connect to vss with a 2.2 f low esr capacitor over all temperature. 14 cvdd - charge pump power supply pin 15 vss2 - ground pin 2 16 vee o negative voltage output pin connect to vss2 with a 1.0 f low esr capacitor over temperature. when this capacitor is polarized, the positive polarity pin should be connected to the vss2 pin. non-polarized cap acitors can also be used. note: all input pins except for the cn, cp, smute and dif pins should not be left floating. ms1196-e-01 2011/03 - 3 -
[AK4430] absolute maximum ratings (vss1=vss2=0v; note 1 ) parameter symbol min max units power supply vdd cvdd -0.3 -0.3 +4.0 +4.0 v v input current (any pins except for supplies) iin - 10 ma input voltage ( note 3 ) vind -0.3 vdd+0.3 v ambient operating temperature ta -20 85 c storage temperature tstg -65 150 c note 1. all voltages with respect to ground. note 2. vss1, vss2 connect to the same analog ground. note 3. smute, mclk, bick, lrck, sdti and dif pins warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (vss1=vss2=0v; note 1 ) parameter symbol min typ max units power supply vdd cvdd +3.0 +3.3 vdd +3.6 v note 4. cvdd should be equal to vdd. *akm assumes no responsibility for the usage beyond the conditions in this datasheet. ms1196-e-01 2011/03 - 4 -
[AK4430] analog characteristics (ta = 25 c; vdd=cvdd = +3.3v; fs = 44.1 khz; bick = 64fs; signal frequency = 1 khz; 24bit input data; measurement frequency = 20hz 20khz; r l 5k , unless otherwise specified) parameter min typ max units resolution 24 bits dynamic characteristics ( note 5 ) fs=44.1khz, bw=20khz - -91 -82 db fs=96khz, bw=40khz - -91 - db thd+n fs=192khz, bw=40khz - -89 - db dynamic range (-60dbfs with a-weighted, note 6 ) 96 104 - db s/n (a-weighted, note 7 ) 96 104 - db interchannel isolation (1khz) 90 104 - db interchannel gain mismatch - 0.2 0.5 db psrr ( note 9 ) 62 db dc accuracy dc offset (at output pin) -5 0 +5 mv gain drift - 100 - ppm/ c output voltage ( note 8 ) 1.85 2.0 2.15 vrms load capacitance ( note 10 ) - - 25 pf load resistance 5 - - k power supplies power supply current: ( note 11 ) normal operation (fs 96khz) normal operation (fs=192khz) power-down mode ( note 12 ) 20 22 10 28 31 100 ma ma a note 5. measured by audio precision (system two). refer to the evaluation board manual. note 6. 98db for 16-bit input data note 7. s/n does not depend on input data length. note 8. full-scale voltage (0db). output voltage is proportional to the voltage of vdd aout (typ.@0db) = 2vrms vdd/3.3. note 9. psrr is applied to vdd and cvdd with 1khz, 50mvpp. note 10. in case of driving capacitive load, inset a resistor between the output pin and the capacitive load. note 11. the current into vdd and cvdd. note 12. all digital inputs including clock pins (mclk, bick and lrck) are fixed to vss or vdd. ms1196-e-01 2011/03 - 5 -
[AK4430] filter characteristics (ta = 25 c; vdd=cvdd = +3.0 +3.6v; fs = 44.1 khz) parameter symbol min typ max units digital filter passband 0.05db ( note 13 ) -6.0db pb 0 - 22.05 20.0 - khz khz stopband ( note 13 ) sb 24.1 khz passband ripple pr 0.01 db stopband attenuation sa 64 db group delay ( note 14 ) gd - 24 - 1/fs de-emphasis filter digital filter + lpf frequency response(1khz reference) fs=44.1khz, 20hz ~ 20.0khz fs=96khz, 20hz ~ 40.0khz fs=192khz, 20hz ~ 80.0khz fr fr fr - - - 0.05 0.05 0.05 - - - db db db note 13. the passband and stopband frequencies scale with fs (system sampling rate). for example, pb=0.4535fs (@ 0.05db), sb=0.546fs. note 14. calculated delay time caused by the digital f ilter. this time is measured from setting the 16/24bit data of both channels to input register to the output of the analog signal. dc characteristics (ta = 25 c; vdd=cvdd = +3.0 +3.6v) parameter symbol min typ max units high-level input voltage low-level input voltage vih vil 70%vdd - - - - 30%vdd v v input leakage current ( note 15 ) iin - - 10 a note 15. the smute pin and dif pin are not included. the smute pin has an internal pull-down resistor (typ.100k ? ) and the dif pin has an internal pull-up resistor (typ. 100k ? ). ms1196-e-01 2011/03 - 6 -
[AK4430] switching characteristics (ta = 25 c; vdd=cvdd = +3.0 +3.6v) parameter symbol min typ max units master clock frequency duty cycle fclk dclk 4.096 40 - 36.864 60 mhz % lrck frequency normal speed mode double speed mode quad speed mode duty cycle fsn fsd fsq duty 8 32 120 45 48 96 192 55 khz khz khz % audio interface timing bick period normal speed mode double speed mode quad speed mode bick pulse width low pulse width high bick ? ? to lrck edge ( note 16 ) lrck edge to bick ? ? ( note 16 ) sdti hold time sdti setup time tbck tbck tbck tbckl tbckh tblr tlrb tsdh tsds 1/128fsn 1/64fsd 1/64fsq 30 30 20 20 20 20 ns ns ns ns ns ns ns ns ns note 16. bick rising edge must not occur at the same time as lrck edge. ms1196-e-01 2011/03 - 7 -
[AK4430] timing diagram 1/fclk tclkl vih tclkh mclk vil dclk=tclkh x fclk, tclkl x fclk 1/fs vih lrck vil tbck tbckl vih tbckh bick vil figure 1. clock timing tlrb lrck vih bick vil tsds vih sdti vil tsdh vih vil tblr figure 2. serial interface timing ms1196-e-01 2011/03 - 8 -
[AK4430] operation overview system clock the external clocks required to operate the AK4430 are mc lk, lrck, and bick. the master clock (mclk) should be synchronized with lrck, but the phase is not critical. the mclk is used to operate the digital interpolation filter and the delta-sigma modulator. sampling speed and mclk frequency are detected automatically, and then the internal master clock is set to the appropriate frequency ( table 1 ). the AK4430 is automatically placed in power saving mode when mclk, lrck and bick stop during normal operation mode, and the analog output goes to 0v(typ). when mclk, lrck and bick are input again, the AK4430 is powered up. after exiting reset following power-up, the AK4430 is not fully operational until mclk, lrck and bick are input. lrck mclk (mhz) fs 128fs 192fs 256fs 384fs 512fs 768fs 1152fs sampling speed 32.0khz - - - - 16.3840 24.5760 36.8640 44.1khz - - - - 22.5792 33.8688 - 48.0khz - - - - 24.5760 36.8640 - normal 32.0khz 8.192 12.288 44.1khz 11.2896 16.9344 48.0khz 12.288 18.432 88.2khz - - 22.5792 33.8688 - - - 96.0khz - - 24.5760 36.8640 - - - double 176.4khz 22.5792 33.8688 - - - - - quad 192.0khz 24.5760 36.8640 - - - - - table 1. system clock example when mclk= 256fs/384fs, the auto setting m ode supports sampling rate of 32khz~96khz ( table 1 ). however, when the sampling rate is 32khz~48khz, dr and s/n will degrade as compared to when mclk= 512fs/768fs ( table 2 ). mclk dr,s/n 256fs/384fs 101db 512fs/768fs 104db table 2. relationship between mclk frequency and dr, s/n (fs= 44.1khz) audio serial interface format the audio data is shifted in via the sdti pin using the bick and lrck inputs. the AK4430 supports two formats as shown in table 3 . the serial data is msb-first, two?s complement format and it is latched on the rising edge of bick. it can be used for 16/20 bit i 2 s formats by zeroing the unused lsbs. mode dif pin sdti format bick figure 0 l 24bit msb justified 48fs figure 3 1 h 24bit i 2 s figure 4 48fs table 3. audio data format ms1196-e-01 2011/03 - 9 -
[AK4430] lrck bick ( 64fs ) sdti 02 2 1 2 24 31 0 1 31 0 1 23:msb, 0:lsb 22 1 0 don?t care 23 lch data rch data 23 30 22 22 4 23 30 22 1 0 don?t care 23 22 23 figure 3. mode 0 timing lrck bick ( 64fs ) sdti 03 1 2 24 31 0 1 31 0 1 23:msb, 0:lsb 22 1 0 don?t care 23 lch data rch data 23 25 3 22 4 23 25 22 1 0 don?t care 23 23 figure 4. mode 1 timing analog output block the internal negative power supply generation circuit ( figure 5 ) provides a negative power supply for the internal 2vrms amplifier. it allows the AK4430 to output an audio signal centered at vss (0v, typ) as shown in figure 6 . the negative power generation circuit ( figure 5 ) needs 1.0uf capacitors (ca, cb) with low esr (equivalent series resistance). if this capacitor is polarized, the positive polarity pin should be connected to the cp and vss2 pins. this circuit operates by clocks generated from mclk. when mc lk stops, the AK4430 is placed in rese t mode automatically and the analog outputs settle to vss (0v, typ). cvdd charge pump cp cn vss2 vee 1uf 1uf negative power a k4 4 30 (+) cb ca (+) figure 5. negative power generation circuit ms1196-e-01 2011/03 - 10 -
[AK4430] a outr a k4430 ( aoutl ) 0v 2vrms figure 6. audio signal output soft mute operation soft mute operation is performed in the digital domain. when the smute pin is set ?h?, the output signal is attenuated to - in 1024 lrck cycles. when the smute pin is returned to ?l?, the mute is cancelled and the output attenuation gradually changes to 0db in 1024 lrck cycles. if the soft mu te is cancelled within the 1024 lrck cycles after starting this operation, the attenuation is disconti nued and it is returned to 0db by the sa me cycle. soft mute is effective for changing the signal source without stopping the signal transmi ssion. in one cycle of lrck, eight ?h? pulses or more must not be input to the smute pin. smute pin attenuation 1024/fs 0db - aout 1024/fs gd gd (1) (2) (3) notes: (1) the time for input data attenuation to - is : normal speed mode: 1024 lrck cycles (1024/fs). double speed mode: 2048 lrck cycles (2048/fs). quad speed mode : 4096 lrck cycles (4096/fs). (2) the analog output corresponding to a speci fic digital input has a group delay, gd. (3) if soft mute is cancelled before attenuating to - after starting the operation, th e attenuation is discontinued and returned to 0db in the same cycle. figure 7. soft mute function ms1196-e-01 2011/03 - 11 -
[AK4430] system reset the AK4430 is in power down mode upon power-up. the mlck s hould be input after the power supplies are ramped up. the AK4430 is in power-down mode until lrck are input. d/a out (analog) mclk 20 us low power supply (vdd, cvdd) 2, 3 lrck digital circuit analog circuit charge pump circuit charge pump counter circuit time a (1) (2) (3) power-up power-up ?0? data d/a in ( di g ital ) mute ( d/a out ) (4) (5) power down power down power-up power down notes: (1) approximately 20us after a mclk input is det ected, the internal analog circuit is powered-up. (2) the digital circuit is powered-up after 2 or 3 lrck cycles following the detection of mclk. (3) the charge pump counter starts after the charge pump ci rcuit is powered-up. the dac outputs a valid analog signal after time a. time a =176/fs: normal speed mode time a =352/fs: double speed mode time a =704/fs: quad speed mode (4) no audible click noise occurs under normal conditions. (5) the power supply must be powered-up when the mclk pin is ?l?. mclk must be input after 20us when the power supply voltage achieves 80% of vdd. if not, click noise may occur at different time from this figure. figure 8. system reset diagram ms1196-e-01 2011/03 - 12 -
[AK4430] reset function when the mclk or lrck or bick stops, the AK4430 is placed in reset mode and its analog outputs are set to vss (0v, typ). when the mclk and lrck, bick are restarted, the AK4430 returns to normal operation mode. normal operation internal state reset normal operation d/a out (analog) d/a in (digital) clock in mclk, bick, lrck (2) vss (3) mclk or bic k or lrck sto p (4) (4) (1) notes: (1) clocks (mclk, bick, lrck) can be stopped in the reset mode (mclk, lrck or bick is stopped). (2) digital data can be stopped. the click noise after mclk , lrck and bick are input again can be reduced by inputting the ?0? data during this period. (3) digital data is muted for about 180/fs (in normal speed mode) from the timing when a clock starts, and then the analog data is output after gd. (4) no audible click noise o ccurs under normal conditions. figure 9. reset timing example ms1196-e-01 2011/03 - 13 -
[AK4430] system design figure 10 shows the system connection diagram. an evaluation boa rd (akd4430) is available for fast evaluation as well as suggestions for peripheral circuitry. analog 3.3v 24bit audio data 1u (1) 64fs master clock analog ground digital ground mode- setting AK4430 dif sdti bick mclk smute cp cn lrck aoutr aoutl vdd vss1 vrefh cvdd vss2 vee 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 + + fs 1u (1) 0.1u 10u + 0.1u 10u lch out rch out + 2.2u (1) + figure 10. typical connection diagram note: (1) use low esr (equivalent series resistance) capacito rs. when using polarized capacitors, the positive polarity pin should be connected to the cp, vss2 and vrefh pins. (2) vss1 and vss2 should be sepa rated from digital system ground. (3) digital input pins should not be allowed to float. ms1196-e-01 2011/03 - 14 -
[AK4430] 1. grounding and power supply decoupling vdd and cvdd are supplied from the analog supply and should be separated from the system digital supply. decoupling capacitors, especially 0.1 f ceramic capacitors for high frequency bypass, should be placed as near to vdd and cvdd as possible. the vss1 and vss2 must be connected to the same analog ground plane. power-up sequence between vdd and cvdd is not critical. 2. analog outputs the analog outputs are single-ended and centered at the vss (ground) voltage. the output signal range is typically 2.0vrms (typ @vdd=3.3v). the internal switched-capacitor filter (scf) and continuous-time filter (ctf) attenuate the noise generated by the delta-sigma modulator beyond the audio passband. using single a 1 st -order lpf ( figure 11 ) can reduce noise beyond the audio passband. the output voltage is a positive full scale for 7fffffh (@24bit data) and a negative full scale for 800000h (@24bit data). the ideal output is 0v (vss) voltage for 000000h (@24bit data). the dc offset is 5mv or less. aout 470 2.2nf ak44 30 2.0vrms (typ) analog out (fc = 154khz, gain = -0.28db @ 40khz, gain = -1.04db @ 80khz) figure 11. external 1 st order lpf circuit example ms1196-e-01 2011/03 - 15 -
[AK4430] package 0-10 detail a seating plane 0.10 0.17 0.05 0.22 0.1 0.65 *5.0 0.1 1.1 (max) a 1 8 9 16 16pin tssop (unit: mm) *4.4 0.1 6.4 0.2 0.5 0.2 0.1 0.1 note: dimension "*" does not include mold flash. 0.13 m package & lead frame material package molding compound: epoxy , halogen (bromine and chlorine) free lead frame material: cu lead frame surface treatment: solder (pb free) plate ms1196-e-01 2011/03 - 16 -
[AK4430] marking akm 4430et xxyyy 1) pin #1 indication 2) date code : xxyyy (5 digits) xx: lot# yyy: date code 3) marketing code : 4430et 4) asahi kasei logo date (yy/mm/dd) revision history revision reason page contents 10/05/31 00 first edition 11/03/01 01 error correction 15 1. gr ounding and power supply decoupling the description was changed. ms1196-e-01 2011/03 - 17 -
[AK4430] important notice z these products and their specifications ar e subject to change without notice. when you consider any use or application of these produc ts, please make inquiries the sales office of asahi kasei microdevices corporation (akm) or authorized dist ributors as to current status of the products. z descriptions of external circuits, a pplication circuits, software and other related inform ation contained in this document are provided only to illustrate the operation and application examples of th e semiconductor products. you are fully responsible for the incorporati on of these external circuits, applicati on circuits, software and other related information in the design of your e quipments. akm assumes no responsibility for any losses incurred by you or third parties arising from the use of these information herein . akm assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of su ch information contained herein. z any export of these products, or devices or systems containi ng them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. z akm products are neither intended nor aut horized for use as critical components note1) in any safety, life support, or other hazard related device or system note2) , and akm assumes no responsibility for such use, except for the use approved with the express written consent by re presentative director of akm. as used here: note1 ) a critical component is one whose failure to functi on or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2 ) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aeros pace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akm products , who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the a bove content and conditions, and the buyer or distributor agrees to assume any and all responsib ility and liability for and hold akm harmless from any and all claims arising from the use of said produc t in the absence of such notification. ms1196-e-01 2011/03 - 18 -

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